The project aims at developing a framework and a related methodology for the dependability analysis and simulation of networked embedded systems targeting, particularly, safety and robustness. These two aspects are very relevant, in particular, for embedded systems used in critical environment, like for example in the automotive field where the goal of leader vendors (e.g., STMicroelectronis) is to produce systems with a failure rate of 1-10 failures per hour.
The framework will be based on an hardware/software/network co-simulation environment (HSN) and on an automatic test pattern generator (Laerte++) under development by UNIVR, and on a mutation analysis tool developed by Certess (Certitude).
The main goal of the project consists of mapping the existent mutation models implemented by Certitude in real faults that may affect the design and production of networked embedded systems, and in the definition of new mutation models for addressing design error identification (safety) and fault tolerance (robustness). Finally, effective strategies for speeding up the mutation analysis process will be developed, and a parallel fault simulator (PAE) will be implemented to be integrated with Certess and Laerte++.
In this context, HSN will be used to model the behaviour of networked embedded systems at different abstraction levels in order to evaluate the effect of modelled faults.
The effectiveness of the framework will be demonstrated by evaluating the dependability of real embedded systems, used in automotive, provided by IC vendors identified by Certess.
